Hard Processor System Component Reference Manual: Agilex™ 5 SoCs
ID
813752
Date
8/15/2025
Public
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H)
5. Design Guidelines
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.3.1. Configurations for HPS IP
2.3.2. Configurations for HPS EMIF IP
2.3.3. Graphical Connections of HPS to HPS-EMIF
2.3.4. Configuration when using ECC
2.3.5. Configuration of HPS EMIF Calibration Settings
2.3.6. Supported Memory Protocols Among Device Families
2.3.7. IO96 Bank and Lane Usage for HPS EMIF
2.3.8. Quartus Report of I/O Bank Usage
2.3.9. Debugging with the External Memory Interface Debug Toolkit
3.1.3.1. QuestaSim* Simulation Steps
- Locate your top-level simulation model, TopLevel.v or TopLevel.vhdl, which you have created.
- Locate it at <project directory>/<Platform Designer design name>/sim/.
- In this directory, name the file as TopLevel.v or TopLevel.vhdl that was created when you previously click the Generate button.
- Locate the msim_setup.tcl script and execute the simulator in the <project directory>/<Platform Designer design name>/sim/mentor/.
- Create a new file my_msim_setup.do and write the following content to the file.
source <path_to>/msim_setup.tcl dev_com com vlog <compilation_options> <design_top_level_vfile> # example: vlog -timescale 1ps/1ps ../TopLevel.v set TOP_LEVEL_NAME <design_top_level_name> # example: set TOP_LEVEL_NAME TopLevel set USER_DEFINED_ELAB_OPTIONS <elaboration options> (optional) elab run -a exit -code 0 (optional)
Refer to VSIM Command Line Aliases and Variables for more information about the vsim aliases and variables. - Set up your developer environment with the proper resources. The Questa* Intel® FPGA Starter Edition is free, but it requires a zero-cost license.
- Run the simulation script.
vsim -do my_msim_setup.do
Since no testbench is added, it only shows that all the HPS IP simulation files were successfully compiled and elaborated using vsim.