Hard Processor System Component Reference Manual: Agilex™ 5 SoCs
ID
813752
Date
8/15/2025
Public
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H)
5. Design Guidelines
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.3.1. Configurations for HPS IP
2.3.2. Configurations for HPS EMIF IP
2.3.3. Graphical Connections of HPS to HPS-EMIF
2.3.4. Configuration when using ECC
2.3.5. Configuration of HPS EMIF Calibration Settings
2.3.6. Supported Memory Protocols Among Device Families
2.3.7. IO96 Bank and Lane Usage for HPS EMIF
2.3.8. Quartus Report of I/O Bank Usage
2.3.9. Debugging with the External Memory Interface Debug Toolkit
4.4.1. Questa* Intel® FPGA Edition Simulation Steps
- Use the following command to change directory to the Mentor Graphics* testbench simulation directory: cd <project directory>/simple_tb/simple_tb/sim/mentor/.
- Create a new file and name it my_msim_setup.do . Edit the file with the following content:
set TOP_LEVEL_NAME simple_tb ### set QSYS_SIMDIR <script generation output directory> set QSYS_SIMDIR ./.. ### source msim_setup.tcl source $QSYS_SIMDIR/mentor/msim_setup.tcl ##ensure_lib ./libraries/ ##ensure_lib ./libraries/work/ ##vmap work ./libraries/work/ ##vmap work_lib ./libraries/work/ ### Compile dev_com com ##vlib work vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../my_simple_tb.sv vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_lwh2f.sv vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_h2f.sv vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_f2sdram.sv vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_f2h.sv ### Simulate elab_debug ###add wave * ###do wave.do ### LWH2F add wave -group LWH2F /simple_tb/simple_inst/intel_agilex_5_soc_0/intel_agilex_5_soc_0/sm_hps/sundancemesa_hps_inst/lwh2f_bfm_gen/lwh2f_axi4_master_inst/* ### H2F add wave -group H2F /simple_tb/simple_inst/intel_agilex_5_soc_0/intel_agilex_5_soc_0/sm_hps/sundancemesa_hps_inst/h2f_bfm_gen/h2f_axi4_master_inst/* ### F2SDRAM add wave -group F2SDRAM_mgr /simple_tb/simple_inst/axi4_mm_manager_intf_0/axi4_mm_manager_intf_0/* add wave -group F2SDRAM_sub /simple_tb/simple_inst/intel_agilex_5_soc_0/intel_agilex_5_soc_0/sm_mpfe/sundancemesa_mpfe_inst/f2sdram_bfm_gen/f2sdram_axi4_slave_inst/* ### F2H add wave -noupdate -group F2H_mgr /simple_tb/simple_inst/ace5lite_bfm_mm_manager_0/ace5lite_bfm_mm_manager_0/* add wave -noupdate -group F2H_sub /simple_tb/simple_inst/intel_agilex_5_soc_0/intel_agilex_5_soc_0/sm_mpfe/sundancemesa_mpfe_inst/f2soc_bfm_gen/f2h_ace5lite_slave_inst/* ### Run the simulation. run -all
- Set up your developer environment with the proper resources. The Questa* Intel® FPGA Starter Edition is free, however it requires a zero-cost license.
- Run the simulation script by being in the Mentor Graphics* testbench simulation directory and executing the simulation command:
- cd <project directory>/simple_tb/simple_tb/sim/mentor/
- vsim -do my_msim_setup.do
The following shows the simulation output from this example.Figure 55. Example of Simulation Output