Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 4/01/2024
Public

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2.2.13.2. User Calibration

The I/O PLL must be recalibrated for any of the following conditions after device power up:

  • Dynamic I/O PLL reconfiguration that changes the M or N counter settings is performed.
  • Change of the reference clock frequency to the I/O PLL.

Recalibration is not necessary when using clock switchover to a secondary reference clock with a different frequency than the primary reference clock. The I/O PLL stores the calibration settings for both reference clocks after power-up calibration.