Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 4/01/2024
Public

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2.2.4. PLL Architecture

Figure 10. I/O Bank I/O PLL High-Level Block Diagram for Agilex™ 5 Devices
Figure 11. Fabric-Feeding I/O PLL High-Level Block Diagram for Agilex™ 5 Devices
Note:
  1. The dedicated clock inputs can feed only one PLL through the dedicated clock path. To feed the second PLL, the clock must be routed onto a global clock network.
  2. If a global reference clock source is required, this clock must be promoted using the Assignment Editor to promote the PLL refclk to a global signal.
  3. inclk1 is not available for fabric-feeding I/O PLL located in HVIO block since clock switchover feature is not supported.