Visible to Intel only — GUID: shv1683683848014
Ixiasoft
1. Agilex™ 5 Clocking and PLL Overview
2. Agilex™ 5 Clocking and PLL Architecture and Features
3. Agilex™ 5 Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. Document Revision History for the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
Visible to Intel only — GUID: shv1683683848014
Ixiasoft
5.2.1. IOPLL IP Core Parameters - PLL Tab
Parameter | Value | Description |
---|---|---|
Device Family | Agilex 5 | Specifies the device family. |
Component | — | Specifies the targeted device. |
Speed Grade | — | Specifies the speed grade for targeted device. |
Reference Clock Frequency | — | Specifies the input frequency for the input clock, refclk, in MHz. The default value is 100.0 MHz. The minimum and maximum value is dependent on the selected device. |
Enable Locked Output Port | On or Off | Turn on to enable the locked port. |
Enable physical output clock parameters | On or Off | Turn on to enter physical PLL counter parameters instead of specifying a desired output clock frequency. |
Compensation Mode | direct, external feedback, normal, source synchronous, zero delay buffer, or lvds | Specifies the operation of the PLL. The default operation is direct mode.
|
Compensated Outclk 13 | 0–6 | Allows you to select which output clock (outclk) to be compensated. The feedback mode compensates for the clock network delay of the outclk selected. This feedback mode ensures correct phase relationship between I/O PLL input and output clocks only for the selected outclk. |
Use Non-dedicated Feedback Path | On or Off | Turn on to conserve clock resources and improve timing analysis. However, this feature creates frequency limitations and disables phase shift. |
Number of Clocks | 1–7 (fabric-feeding), 1–4 (I/O bank) | Specifies the number of output clocks required for each device in the PLL design. The requested settings for output frequency, phase shift, and duty cycle are shown based on the number of clocks selected. |
Multiply Factor (M-Counter) 14 | 4–320 | Specifies the multiply factor of M-counter. |
Divide Factor (N-Counter) 14 | 1–110 | Specifies the divide factor of N-counter. |
Specify VCO Frequency | On or Off | Allows you to restrict the VCO frequency to the specified value. This is useful when creating a PLL for LVDS external mode, or if a specific dynamic phase shift step size is desired. |
Desired VCO Frequency 15 | — | Specifies the VCO frequency for the PLL in MHz. The default value is 600.0 MHz. |
Actual VCO Frequency | — |
|
Give clock global name | On or Off | Allows you to rename the output clock name. |
Clock Name | — | The user clock name for Synopsis Design Constraints (SDC). |
Divide Factor (C-Counter) 14 | 1–510 | Specifies the divide factor for the output clock (C-counter). |
Desired Frequency | — | Specifies the output clock frequency of the corresponding output clock port, outclk[], in MHz. The default value is 100.0 MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places. |
Actual Frequency | — | Allows you to select the actual output clock frequency from a list of achievable frequencies. The default value is the closest achievable frequency to the desired frequency. |
Phase Shift units | ps or degrees | Specifies the phase shift unit for the corresponding output clock port, outclk[], in picoseconds (ps) or degrees. |
Desired Phase Shift | — | Specifies the requested value for the phase shift. The default value is 0 ps. |
Actual Phase Shift | — | Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift. |
Desired Duty Cycle | 0.1–100.0 | Specifies the requested value for the duty cycle. The default value is 50.0%. |
Actual Duty Cycle | — | Allows you to select the actual duty cycle from a list of achievable duty cycle values. The default value is the closest achievable duty cycle to the desired duty cycle. |
14 This parameter is only available when Enable physical output clock parameters is turned on.
15 This parameter is only available when Specify VCO Frequency is turned on and Enable physical output clock parameters is turned off.