Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.12. PLL Reconfiguration and Dynamic Phase Shift

Agilex™ 5 devices support PLL reconfiguration and dynamic phase shift with the following features:

  • PLL reconfiguration—I/O PLL can reconfigure a collection of parameters such as M, N, and C counter, bandwidth, and charge pump.
  • Dynamic phase shift—I/O PLL can perform positive or negative phase shift. Able to shift multiple phase steps each time, where one phase step is equal to 1/8 of the VCO period. Dynamic Phase Shifts can only be performed through PLL reconfiguration.