Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 4/01/2024
Public

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5.2.4. IOPLL IP Core Parameters - Advanced Parameters Tab

Table 11.   IOPLL IP Core Parameters - Advanced Parameters Tab for Agilex™ 5 Devices
Parameter Value Description
Advanced Parameters Displays a table of physical PLL settings that are implemented based on your input.

I/O bank I/O PLL supports a maximum of 4 output clocks. The IOPLL IP core implements the output clocks using C0 to C3 counters.

Fabric-feeding I/O PLL supports a maximum of 7 output clocks. The IOPLL IP core implements the output clocks using C0 to C6 counters.

Table 12.  Output Clocks and C Counters Mapping
Output Clock C Counter
outclk0 C0
outclk1 C1
outclk2 C2
outclk3 C3
outclk4 C4
outclk5 C5
outclk6 C6