Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 4/01/2024
Public

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Document Table of Contents

1.2. PLLs Overview

Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Agilex™ 5 device family contains the following I/O PLLs for core applications. The I/O PLLs can only function as integer PLLs.

  • Fabric-feeding I/O PLLs—seven C counter outputs available and support PLL cascading. However, Fabric-feeding I/O PLL to Fabric-feeding I/O PLL cascading is not supported.
  • I/O bank I/O PLLs—four C counter outputs available and support PLL cascading
The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the HSIO I/O banks. Each HSIO I/O bank contains two I/O bank I/O PLLs and one fabric-feeding I/O PLL, whereas each HVIO block contains one fabric-feeding I/O PLL.
Note: The fabric-feeding I/O PLL located in HVIO block does not support PLL cascading or clock switchover.