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1. Agilex™ 5 Clocking and PLL Overview
2. Agilex™ 5 Clocking and PLL Architecture and Features
3. Agilex™ 5 Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. Document Revision History for the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Clocking Constraints
3.6. IP Core Constraints
3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
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1.2. PLLs Overview
Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.
The Agilex™ 5 device family contains the following I/O PLLs for core applications. The I/O PLLs can only function as integer PLLs.
- Fabric-feeding I/O PLLs—seven C counter outputs available and support PLL cascading. However, Fabric-feeding I/O PLL to Fabric-feeding I/O PLL cascading is not supported.
- I/O bank I/O PLLs—four C counter outputs available and support PLL cascading
The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the HSIO I/O banks. Each HSIO I/O bank contains two I/O bank I/O PLLs and one fabric-feeding I/O PLL, whereas each HVIO block contains one fabric-feeding I/O PLL.
Note: The fabric-feeding I/O PLL located in HVIO block does not support PLL cascading or clock switchover.