Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 4/01/2024
Public

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2.2.10. PLL Cascading

Agilex™ 5 devices support PLL-to-PLL cascading. You can cascade a maximum of two PLLs. PLL cascading synthesizes more output clock frequencies than a single PLL.

Agilex™ 5 devices support the following PLL-to-PLL cascading modes for I/O bank I/O PLL and I/O Bank Fabric-Feeding I/O PLL. HVIO fabric-feeding I/O PLL do not support cascading.
  • I/O Bank I/O-PLL-to-I/O Bank I/O-PLL cascading
  • I/O Bank I/O-PLL-to-I/O Bank fabric-feeding I/O-PLL cascading
  • I/O Bank fabric-feeding I/O-PLL-to I/O Bank I/O-PLL cascading
Cascading of PLLs can be done via two paths: via dedicated cascade path or via core clock fabric.
  • Cascading via dedicated cascade path—upstream I/O PLL and downstream I/O PLL must be in the same I/O column and are placed adjacently.
  • Cascading via core clock fabric—no restriction on locations of upstream and downstream I/O PLL.

The permit_cal input of the downstream I/O PLL must be connected to the locked output of the upstream I/O PLL in both PLL cascading modes.

The following figures show the connectivity required between the upstream and downstream I/O PLL for both the PLL cascading modes.

Figure 18. I/O-PLL-to-I/O-PLL Cascading Through Dedicated Cascade Path
Note: To set up an I/O bank I/O PLL as the upstream PLL, you must enable up to 6 or 7 counters as only C5 and C6 can be the cascade_out port. You can leave the unused counters disconnected.
Figure 19. I/O-PLL-to-I/O-PLL Cascading Through Core Clock Fabric