AN 977: Nios® V Processor Custom Instruction

ID 773194
Date 4/14/2023
Document Table of Contents

2.2.2. Multicycle Custom Instruction Timing

On the first clock cycle of the custom instruction execution, the processor asserts the active high enable port. Simultaneously, the data0, data1, and alu_result ports have valid values and remain valid for the duration of the custom instruction execution. The enable signal is asserted for a single clock cycle.

The processor waits until the active high done signal is asserted. The processor reads the result port on the same clock edge on which done is asserted. The custom logic block must present data on the result port on the same clock cycle on which it asserts the done signal.
Figure 5. Multicycle Custom Instruction Timing Diagram