AN 977: Nios® V Processor Custom Instruction

ID 773194
Date 4/14/2023
Document Table of Contents

1. Nios® V Processor Custom Instruction Overview

Custom instructions allow you to customize the Nios® V processor to meet the needs of a particular application. You can accelerate time-critical software algorithms by converting them into custom hardware logic blocks. Custom instructions provide an easy way to experiment with hardware-software tradeoffs at any point in the design process because you can easily alter the design of the FPGA-based Nios® V processor.

The custom instruction logic connects to the Nios® V processor arithmetic logic unit (ALU) as shown in the following figure. The feature is available in the Nios® V/g processor variant only.
Figure 1. Custom Instruction Logic Connections to the Nios® V Processor ALU

The Nios® V processor custom instruction does not support the following operations:

  • Branch operations
  • Read or write Control and Status Registers (CSRs)
  • Modify processor cache