AN 977: Nios® V Processor Custom Instruction

ID 773194
Date 4/14/2023
Document Table of Contents

4.3.5. Adding the Custom Instruction HDL File

To specify the synthesis HDL files for your custom instruction, browse to the HDL logic definition files in the design example.

To specify the synthesis files, follow these steps:

  1. Click Next to display the Files tab.
  2. Under Synthesis Files, click Add Files.
  3. Browse to the custom instruction HDL file and click Open.
    Note: The Intel® Quartus® Prime Analysis and Synthesis program checks the design for errors when you add the files. Ensure that no error message appears.
  4. If there are multiple HDL files, follow the steps below. Else, proceed to the next step.
    1. Go to the top-level HDL file.
    2. At the same row, click the Attributes column.
    3. Turn on Top-level File in the File Attributes window.
    4. Click OK.
  5. Click Analyze HDL Files to synthesize the top-level file.
  6. To simulate the system, you can add your simulation files under Verilog Simulation Files or VHDL Simulation Files in the in the Files tab.
Figure 19. Component Editor – Synthesis Files
Figure 20. Component Editor – Verilog Simulation Files
Figure 21. Component Editor – VHDL Simulation Files