Intel Agilex® 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 4/10/2023

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Document Table of Contents

3.6. IP Core Constraints

To implement the IOPLL IP core, you must adhere to the following constraints:

  • Any SDC design constraints referring to the I/O PLL clocks must be listed after the SDC constraints for the IOPLL IP core.
  • Intel recommends reading the SDC for all I/O PLLs first in a design. You can do this by listing the IP before others in the .qsf file.