Intel Agilex® 7 Clocking and PLL User Guide: M-Series

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ID 769001
Date 4/10/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 FPGA M-Series Clocking and PLL Overview 2. M-Series Clocking and PLL Architecture and Features 3. M-Series Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. Document Revision History for the Intel Agilex® 7 Clocking and PLL User Guide: M-Series
1. Intel Agilex® 7 FPGA M-Series Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. M-Series Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration 2.2.13.3. Static Phase Error Calibration
3. M-Series Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Clocking Constraints 3.6. IP Core Constraints 3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
4. Clock Control Intel® FPGA IP Core x
4.1. Release Information for Clock Control Intel® FPGA IP 4.2. Clock Control IP Core Parameters 4.3. Clock Control IP Core Ports and Signals
5. IOPLL Intel® FPGA IP Core x
5.1. Release Information for IOPLL Intel® FPGA IP 5.2. IOPLL IP Core Parameters 5.3. IOPLL IP Core Ports and Signals
5.2. IOPLL IP Core Parameters x
5.2.1. IOPLL IP Core Parameters - PLL Tab 5.2.2. IOPLL IP Core Parameters - Settings Tab 5.2.3. IOPLL IP Core Parameters - Cascading Tab 5.2.4. IOPLL IP Core Parameters - Advanced Parameters Tab
1. Intel Agilex® 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. Document Revision History for the Intel Agilex® 7 Clocking and PLL User Guide: M-Series

5.3. IOPLL IP Core Ports and Signals

Table 13.   IOPLL IP Core Ports for M-Series Devices
Port Name Type Condition Description
refclk Input Required The reference clock source that drives the I/O PLL.
rst Input Required The asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0.
fbclk Input Optional

The external feedback input port for the I/O PLL.

The IOPLL IP core creates this port when the I/O PLL is operating in external feedback mode or zero-delay buffer mode. To complete the feedback loop, a board-level connection must connect the fbclk port and the external clock output port of the I/O PLL.

fboutclk Output Optional

The port that feeds the fbclk port through the mimic circuitry.

The fboutclk port is available only if the I/O PLL is in external feedback mode.

zdbfbclk Bidirectional Optional

The bidirectional port that connects to the mimic circuitry. This port must connect to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I/O PLL.

The zdbfbclk port is available only if the I/O PLL is in zero-delay buffer mode.

locked Output Optional The IOPLL IP core drives this port high when the PLL acquires lock. The port remains high as long as the I/O PLL is locked. The I/O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals exceeds the lock circuit tolerance, the I/O PLL loses lock.
refclk1 Input Optional Second reference clock source that drives the I/O PLL for clock switchover feature.
extswitch Input Optional Active low signal. Assert the extswitch signal low (1’b0) for at least three clock cycles to manually switch the clock.
activeclk Output Optional Output signal to indicate which reference clock source is in used by I/O PLL.
clkbad Output Optional Output signal that indicates the status of reference clock source is good or bad.
cascade_out Output Optional Output signal that feeds into downstream I/O PLL.
adjpllin Input Optional Input signal that feeds from upstream I/O PLL.
outclk_[] Output Optional Output clock from I/O PLL.
permit_cal Input Optional This is an input port for the downstream I/O PLL. Connect this permit_cal port to the locked output port of the upstream I/O PLL. Connecting this permit_cal port ensures that the cascaded I/O PLLs are calibrated in the correct order.
phout Output Optional Port is enabled after Enable access to PLL DPA output port is turned on. This signal can be configured by turning on Specify VCO frequency in the PLL and specifying the VCO frequency value.
outclk_periph Output Optional

Port is enabled after Enabled access to I/O Bank clock ports is turned on. This signal indicates the output clocks for the periphery, e.g. LVDS. The clock can only be connected to one LVDS only.

Enables this parameter in case the PLL feeds an LVDS SERDES block with external PLL.
phout_periph Output Optional

Port is enabled after Enabled access to I/O Bank clock ports is turned on. This signal indicates VCO clock that gets routed throughout periphery. The clock port can only be connected to one LVDS.

Enables this parameter in case the PLL feeds an LVDS SERDES block with external PLL.
Cal_bus_address Input Optional AVL interface address port from IOSSM.
Cal_bus_clk Input Optional AVL interface clock from IOSSM.
Cal_bus_read Input Optional AVL interface read enable signal from IOSSM.
Cal_bus_readdata Output Optional AVL interface read data port to IOSSM.
Cal_bus_rst_n Input Optional AVL interface write data port from IOSSM.
Cal_bus_write Input Optional AVL interface write enable signal from IOSSM.
Cal_bus_writedata Input Optional AVL interface write data port from IOSSM.
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