Intel Agilex® 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 4/10/2023

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Document Table of Contents

2.2.3. PLL Locations

Figure 8. I/O PLL Locations in I/O Bank
Figure 9. Fabric-feeding I/O PLL Location In UIBSS

Within an I/O bank, there is a top index sub-bank and a bottom index sub-bank placed near the edge of the die.

If one of the sub-banks is not available in the I/O bank, the dedicated clock input and clock output pins for the I/O PLL located in this unbonded sub-bank are unavailable. However, you can still use the I/O PLL in the following scenarios by ensuring the VCCPT is powered up:

  • PLL cascading and reconfiguration are supported.
  • You may use any available regular I/O pins as clock input and clock output pins for this I/O bank I/O PLL.

If one of the sub-banks is not available in the I/O bank, the fabric-feeding I/O PLL in this I/O bank has only one pair of dedicated clock input pins which is from the available sub-bank. Reconfiguration is supported by this fabric-feeding I/O PLL.

In M-Series devices, there are two fabric-feeding I/O PLLs and a UIB PLL that reside in the UIB subsystem. The UIB PLL is only dedicated for HBM usage and cannot be used for general purpose. As for the two fabric-feeding I/O PLLs at each sides of the UIBSS, it is dedicated for fabric clocking. Although the features supported are almost identical to the fabric-feeding I/O PLL located at the I/O banks , the fabric-feeding I/O PLLs in the UIBSS does not support any form of cascading, reconfiguration and dynamic phase shift.