2.2.7. Clock Multiplication and Division
An M-Series PLL output frequency is related to its input reference clock source by the scale factor: M/(N × C) for I/O PLL.
The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match fin × (M/N). When using non-dedicated feedback path in normal or source synchronous compensation mode, the control loop drives the VCO to match fin × ((M × Ci )/N), where Ci is the compensated outclk C counter value. The Intel® Quartus® Prime software automatically chooses the appropriate scale factors according to the input frequency, multiplication, and division values that you specify in the parameter editor for the IP.
Pre-Scale Counter, N and Multiply Counter, M
Each PLL has one pre-scale counter, N, and one multiply counter, M. The M and N counters do not use duty-cycle control because the only purpose of these counters is to calculate frequency division.
Post-Scale Counter, C
Each output port has a unique post-scale counter, C. For multiple C counter outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. For example, if the output frequencies required from one I/O PLL are 55 MHz and 100 MHz, the Intel® Quartus® Prime software sets the VCO frequency to 1.1 GHz (the least common multiple of 55 MHz and 100 MHz within the VCO operating frequency range). Then the post-scale counters, C, scale down the VCO frequency for each output port.
The I/O PLL can only operate in integer mode.