MACsec Intel® FPGA System Design User Guide

ID 767516
Date 10/02/2023

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Document Table of Contents

2.2.1. Ethernet Subsystem

The E/F-Tile Hard IP is configured in MAC+PCS layer mode. The IP core handles the frame encapsulation and gives out data from the FPGA at the 25Gbps, or 100Gbps line rate. For supporting both 25G and 100G, two different IP instances for 25-Gbps and 100-Gbps are used. One of them is selected at the compile time based on the speed selected. In the transmit direction, the MAC accepts the encrypted frames from the MACsec and inserts the inter-packet gap (IPG), start control, term control, preamble, start of frame delimiter (SFD), padding, and FCS bits before passing them to the PHY.
Figure 5. TX Frame Structure
In the receive direction, the PHY passes frames to the MAC. The MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the user interface that connects to the MACsec IP.
Figure 6. RX Frame Structure