MACsec Intel® FPGA System Design User Guide

ID 767516
Date 10/02/2023

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2.4. Data Path Between MACsec and Packet Generator/Checker (Packet Client)

The path between MACsec and Packet client works in a single clock domain and with the same data bus width matching the Ethernet data rate. Connections between both of the modules are 1:1 mapping. Due to potential future Ethernet rate matching for 100G/200G/400G, packet clients are maintained in HW itself and software functions do not implement data plane termination and sourcing at/from a host. Also MACsec usecases are not limited to the NIC where the packets are terminated at a TCP port. It could be a L2, L3 function or a switch.