MACsec Intel® FPGA System Design User Guide

ID 767516
Date 10/02/2023

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2.4.2. Packet Generation and Check

The packet generation block receives settings like packet mode, packet size, IPG,Idle cycle, packet transfer enable, packet smac and packet dmac address from the packet client CSR, as shown in the figure below. Based on this information, the internal state machine creates packets matching the packet size with incremental payload.
Figure 20. Packet Generator and Checker

This solution enables full duplex data transfers so the patten generation and checking can be similar in both directions. The packet checker received data is compared with the reference data from the packet generator. It increments the error count if the reference data does not match with the received data. The packet checker also includes statistics counters which count the tx_sop,rx_sop,tx_eop and rx_eop signal assertions. If the received and transmitted byte count matches the packet size, then the test done signal gets asserted and produces the packet count on the CSR.

The packet generator supports dynamic packet sizes where subsequent packet sizes increment in size by a programmed value which is defaulted to 1.