MACsec Intel® FPGA System Design User Guide

ID 767516
Date 10/02/2023

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2.2. Data Path Between Ethernet MAC and MACsec

When the Ethernet MAC is configured for 25G/100G, the IP enables the user interface with 64/512 bit data bus respectively. This system reference design scales to 100G full duplex support for Devkits once they are available. The packet generator-checker block supports 100G data rates. Any adaptors in the datapath are modular to achieve these rates. Future releases may include the HSSI Subsystem instead of the E/F-Tile QHIP. This path uses the standard signals from both IP interfaces.