MACsec Intel® FPGA System Design User Guide

ID 767516
Date 10/02/2023
Public

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Document Table of Contents

2.4.1. Packet Client

The packet client has internal FSMs that generate data based on control from the CSR interface. Applications running on the host VMs can customize the design’s data traffic by programming the packet client registers. The host application may also need to pause/stop the packet transfers by using SA retire. The packet client produces AVST data streams which needs to be converted to AXI-ST using bridge adaptors.

Below is an example sequence of the CSR access needed to enable the packet client. Please note that the sequence below does not cover all the available CSR options.
  1. Start Packet client Tx by setting CFG_PKT_CL_CTRL[0] to ‘1’ (offset 0x0, value 0x01).
  2. Wait for data traffic to complete & counters to update.
  3. Set Status Snapshot capture bit by setting CFG_PKT_CL_CTRL[6] to ‘1’ (offset 0x0, value 0x41).
  4. Read Status counters (offsets 0x20 to 0x4C) & verify.
  5. Clear Status Snapshot capture bit by setting CFG_PKT_CL_CTRL[6] to ‘0’ (offset 0x0, value 0x1).
  6. Set CSR Status Clear bit by setting CFG_PKT_CL_CTRL[7] to ‘1’ (offset 0x0, value 0x81).
  7. Clear CSR Status Clear bit by setting CFG_PKT_CL_CTRL[7] to ‘0’ (offset 0x0, value 0x1).
  8. Stop Packet client & clear all internal counters (offset 0x0, value 0x100).