MACsec Intel® FPGA System Design User Guide

ID 767516
Date 10/02/2023

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2.7. Packet FIFO

The Ethernet MAC (TX) as well as the MACsec IP’s uncontrolled ports expect data at a packet boundary and may be unpredictable if the valid goes low in between a packet transfer after the start of the packet and before end of the packet. This can be implemented either on the AVST or AXI streaming interfaces. The figure below shows the implementation for the Avalon streaming (AVST) interface. Every EOP on the input side increments the tracking counter on the output side. Writing data into FIFO happens on a clock cycle boundary, but the reading from FIFO is controlled at the packet boundary. The read enable logic on FIFO read asserts only when the packet counter is non-zero. The packet counter increments by 1 when the EOP is read from the FIFO. The packet counter value does not change when both the increment and decrement flags get asserted in the same clock cycle. The packet FIFO works in a single clock domain.
Figure 25. Single Clock Domain Packet FIFO