Nios® V Processor Software Developer Handbook

ID 743810
Date 5/26/2023
Public

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8.6.3.1. Hardware Interrupt Funnel for the Internal Interrupt Controller

With the Internal Interrupt Controller (IIC), the Nios® V processor supports 16 internal platform interrupts. In the HAL funnel, hardware interrupt 0 has the highest priority, and 15 the lowest. This prioritization is a feature of the HAL funnel, and is not inherent in the IIC.

The hardware interrupt funnel calls the user-registered ISRs. It goes through the hardware IRQs in Machine Interrupt-Pending mip register starting at hardware IRQ0, and finds the first (highest priority) active hardware IRQ. Then it calls the corresponding registered ISR. After this ISR executes, the funnel begins scanning the hardware IRQs again, starting at hardware IRQ0. In this way, higher-priority interrupts are always processed before lower-priority interrupts. When all hardware IRQs are clear, the hardware interrupt funnel returns to the top level.

For more information on applying the hardware interrupts, refer to the Nios V Processor Hardware Interrupt Service Routines chapter.

Figure 16. HAL Hardware Interrupt Funnel for the Internal Interrupt Controller