Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 4/17/2023

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2.4.1. Testbench

Figure 8. Block Diagram of the Design Example Multiport 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS with LVDS I/O Simulation Testbench

A successful testbench sends ten packets and receives the same number of packets. The following sample output illustrates the excerpt of the output:

Figure 9. Simulation Test Result of VCS Simulator

Statistics MAC Tx Path

      — Frames sent in TX path total:      10
      — Tx_good_sent:        10
      — Tx_vlan_sent:         0
      — Tx_stack_vlan_sent:      0
      — Payload_err_sent:        0

Statistics MAC Rx Path — Loopback Test

      — Rx_good_rcvd:        10
      — Rx_vlan_rcvd:         0
      — Rx_stack_vlan_rcvd:      0
      — Rx_fifo_overflow_rcvd:   0
      — Rx_payload_err_rcvd:     0
      — Rx_crc_err_rcvd:         0

-- The total number of good packets received by the traffic monitor:      10

-- The total number of packets received with CRC error:    0

-- Loopback Simulation Ended with no Error

- -------------------------------------------------------------------------- -

End of Simulation — Break

$finish called from file "", line 5380.
$finish at simulation time        327000000000
            V C S  S i m u l a t i o n  R e p o r t
Time: 327000000000 fs
CPU Time:    259.890 seconds;        Data structure size:    9.3Mb