Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 4/17/2023

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2.3.2. Clock and Reset Signals

Table 6.  Clock and Reset Signals
Signal Direction Width Description
ref_clk Input 1 Drives register access reference clock and MAC FIFO status interface clock. Set the clock to 100 MHz.
iopll_refclk Input 1 125 MHz reference clock for the 1.25 Gbps serial LVDS I/O interface.