Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide
ID
741330
Date
4/17/2023
Public
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1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide
1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench
Figure 5. Procedure to Simulate Example Testbench
Follow these steps to simulate the testbench:
- Change to the testbench simulation directory <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
Table 4. Steps to Simulate the Testbench Simulator Instructions ModelSim* In the command line, type vsim -do run_vsim_mac_pcs.do. If you prefer to simulate without bringing up the ModelSim* GUI, type vsim -c -do run_vsim_mac_pcs.do. Synopsys* VCS* / VCS* MX In the command line, type sh run_vcs_mac_pcs.sh or sh run_vcsmx_mac_pcs.sh. Xcelium* In the command line, type sh run_xcelium_mac_pcs.sh. - Analyze the results. The successful testbench sends ten packets, receives the same number of packets, and displays the following message:
End of Simulation - Break