Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

ID 741330
Date 4/17/2023

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1.1. Directory Structure

The Triple-Speed Ethernet Intel® FPGA IP design example file directories contain the following generated files for the 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA:
  • The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
  • The compilation-only design example is located in <design_example_dir>/compilation_test_design.
  • The compilation test and hardware test designs use files in <design_example_dir>/ex_tse/common.
Figure 2. Directory Structure for the Design Example
Table 1.   Triple-Speed Ethernet Intel® FPGA IP Testbench File Description
Directory/File Description
Testbench and Simulation Files
<design_example_dir>/example_testbench/ Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
Testbench Scripts
<design_example_dir>/example_testbench/ The ModelSim script to run the testbench.
<design_example_dir>/example_testbench/ The Synopsys* VCS script to run the testbench.
<design_example_dir>/example_testbench/ The Synopsys* VCS MX script (combined Verilog HDL and System Verilog with VHDL) to run the testbench
<design_example_dir>/example_testbench/ The Xcelium* script to run the testbench.
Table 2.   Triple-Speed Ethernet Intel® FPGA IP Hardware Design Example File Description
Directory/File Description
<design_example_dir>/hardware_test_design/altera_eth_tse_hw.qpf Intel® Quartus® Prime project file.
<design_example_dir>/hardware_test_design/altera_eth_tse_hw.qsf Intel® Quartus® Prime project settings file.
<design_example_dir>/hardware_test_design/altera_eth_tse_hw.sdc Synopsys* Design Constraints files. You can copy and modify these files for your own Intel® Stratix® 10 design.
<design_example_dir>/hardware_test_design/altera_eth_tse_hw.v Top-level Verilog HDL design example file.
<design_example_dir>/hardware_test_design/common/ Hardware design example support files.