HDMI PHY Intel FPGA IP Design Example User Guide

ID 732781
Date 7/20/2022

2.3. Reconfiguration Sequence Flow

Figure 5. Multi-rate Reconfiguration Sequence FlowThe figure illustrates the multi-rate reconfiguration sequence flow of the controller when it receives input data stream and reference clock frequency, or when the transceiver is unlocked.
Figure 6. Reconfiguration Sequence FlowThe figure illustrates the Nios II software flow that involves the controls for I2C master and HDMI TX PHY.

Did you find the information on this page useful?

Characters remaining:

Feedback Message