2.3. Reconfiguration Sequence Flow
Figure 5. Multi-rate Reconfiguration Sequence FlowThe figure illustrates the multi-rate reconfiguration sequence flow of the controller when it receives input data stream and reference clock frequency, or when the transceiver is unlocked.
Figure 6. Reconfiguration Sequence FlowThe figure illustrates the Nios II software flow that involves the controls for I2C master and HDMI TX PHY.
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