HDMI PHY Intel FPGA IP Design Example User Guide

ID 732781
Date 7/20/2022

2.6. Hardware Setup

The HDMI PHY Intel® FPGA IP design example is HDMI 2.0b capable and performs a loop-through demonstration for a standard HDMI video stream.
To run the hardware test, connect an HDMI-enabled device such as a graphics card with HDMI interface to the HDMI RX connector on the Bitec HDMI 2.0 daughter card, which route the data to the transceiver RX block and HDMI RX.
  1. The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
  2. The HDMI RX core decodes the video, auxiliary, and audio data to be looped back via AXI4-stream interface to the HDMI TX core.
  3. The HDMI source port of the FMC daughter card transmits the image to a monitor.
  4. Press the cpu_resetn button once to perform system reset.
Note: If you want to use another Intel FPGA development board, you must change the device assignments and the pin assignments. The transceiver analog setting is tested for the Intel® Arria® 10 FPGA development kit and Bitec HDMI 2.0 daughter card. You may modify the settings for your own board.

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