HDMI PHY Intel FPGA IP Design Example User Guide

ID 732781
Date 7/20/2022

2. HDMI 2.0 PHY Design Example

The HDMI PHY Intel® FPGA IP design example demonstrates one HDMI instance parallel loopback comprising three RX channels and four TX channels, operating at data rates up to 6 Gbps.

The generated HDMI PHY Intel FPGA IP design example is the same as the design example generated in the HDMI Intel FPGA IP core. However, this design example uses the new TX PHY, RX PHY, and PHY arbiter instead of custom RTL in the HDMI Intel FPGA IP core design example.

Figure 3. HDMI 2.0 PHY Design Example
Table 2.  HDMI PHY Components
Module Description
RX PHY The RX PHY recovers serial HDMI data and send this to the HDMI RX core in parallel format on the recovered clock domains (rx_clk[2:0]). The data is decoded into video data to be output via AXI4-stream video. The RX PHY also sends vid_clk and ls_clk signals to the HDMI RX core via the PHY interface.
HDMI TX Core The HDMI TX core receives AXI4-stream video data and encodes this into HDMI format parallel data. The HDMI TX core sends this data to the TX PHY.
HDMI RX Core The IP receives the serial data from the RX PHY and performs data alignment, channel deskew, TMDS decoding, auxiliary data decoding, video data decoding, audio data decoding, and descrambling.
TX PHY Receives and serializes the parallel data from the HDMI TX core and outputs HDMI TMDS streams. The TX PHY produces tx_clk for the HDMI TX core. The TX PHY also generates vid_clk and ls_clk and sends these signals to the HDMI TX core via the PHY interface.
IOPLL Generates 300 MHz AXI serial stream clock for the AXI4-stream interface.
I2C Master To configure the various PCB components.

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