HDMI PHY Intel FPGA IP Design Example User Guide

ID 732781
Date 7/20/2022
Give Feedback

1.1. Generating the Design

Use the HDMI PHY Intel® FPGA IP parameter editor in the Intel® Quartus® Prime software to generate the design examples.
Figure 2. Generating the Design Flow
  1. Create a project targeting Intel® Arria® 10 device family and select the desired device.
  2. In the IP Catalog, locate and double-click Interface Protocols > Audio & Video > HDMI TX PHY Intel® FPGA IP (or HDMI RX PHY Intel® FPGA IP ). The New IP Variant or New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
  4. Click OK. The parameter editor appears.
  5. On the Design Example tab, select Arria 10 HDMI RX-TX Retransmit.
  6. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  7. For Generate File Format, select Verilog or VHDL.
  8. For Target Development Kit, select Intel® Arria® 10 GX FPGA Development Kit. If you select a development kit, then the target device changes to match the device on target board. For Intel® Arria® 10 GX FPGA Development Kit, the default device is 10AX115S2F4I1SG.
  9. Click Generate Example Design.