HDMI PHY Intel FPGA IP Design Example User Guide

ID 732781
Date 7/20/2022

2.5. Clocking Scheme

The following is the clocking scheme of the HDMI PHY Intel® FPGA IP design example:
  • clk_fpga_b3_p is a 100 MHz fixed rate clock for running the NIOS processor and control functions. If the supplied frequency is correct, the user_led_g[1] toggles for every second.
  • refclk_fmcb_p is a fixed rate reference clock for power-up calibration of the transceivers. It is 625 MHz by default but can be of any frequency.
  • fmcb_gbtclk_m2c_p_0 is the TMDS clock for HDMI RX. This clock is also used to drive the HDMI TX transceivers. If the supplied frequency is 148.5 MHz, the user_led_g[0] toggles for every second.

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