1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
2.8. Optimizing Platform Designer System Performance
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from On-Chip Flash (UFM)
4.6. Nios® V Processor Booting from General Purpose QSPI Flash
4.7. Nios® V Processor Booting from Configuration QSPI Flash
4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.10. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.11. Reducing Nios® V Processor Booting Time
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
4.5.3.1. Hardware Design Flow
The following section describes a step-by-step method for building a bootable system for a Nios® V processor application copied from On-Chip Flash to RAM using boot copier. The example below is built using MAX® 10 device.
IP Component Settings
- Create your Nios® V processor project using Quartus® Prime and Platform Designer.
- Make sure external RAM or On-Chip Memory (OCRAM) is added to your Platform Designer system.
Figure 53. Example IP Connections in Platform Designer for Booting Nios® V Processor from On-Chip Flash (UFM)
- In the On-Chip Flash IP parameter editor, set the Configuration Mode to one of the following, according to your design preference:
- Single Uncompressed Image
- Single Compressed Image
- Single Uncompressed Image with Memory Initialization
- Single Compressed Image with Memory Initialization
For Dual Compressed Images, refer to the MAX® 10 FPGA Configuration User Guide - Remote System Upgrade for more information.Note: You must assign Hidden Access to every CFM regions in the On-Chip Flash IP.
Figure 54. Configuration Mode Selection in On-Chip Flash Parameter Editor
On-Chip Flash IP Settings - UFM Initialization
You can choose one of the following methods according to your preference:
Note: The steps in the subsequent subchapters (Software Design Flow and Hardware Design Flow) depend on the selection you make here.
- Method 1: Initialize the UFM data in the SOF during compilation
Quartus® Prime includes the UFM initialization data in the SOF during compilation. SOF recompilation is needed if there are changes in the UFM data.
- Check Initialize flash content and Enable non-default initialization file.
Figure 55. Initialize Flash Contents and Enable Non-default Initialization File
- Specify the path of the generated .hex file (from the elf2hex command and riscv32-unknown-elf-objcopy) in the User created hex or mif file.
Figure 56. Adding the .hex File Path
- Check Initialize flash content and Enable non-default initialization file.
-
Method 2: Combine UFM data with a compiled SOF during POF generation
UFM data is combined with the compiled SOF when converting programming files. You do not need to recompile the SOF, even if the UFM data changes. During development, you do not have to recompile SOF files for changes in the application. Altera® recommends this method for application developers.
- Uncheck Initialize flash content..
Figure 57. Initialize Flash Content with Non-default Initialization File
- Uncheck Initialize flash content..
Reset Agent Settings for Nios® V Processor Boot-copier Method
- In the Nios® V processor parameter editor, set the Reset Agent to On-Chip Flash.
Figure 58. Nios® V Processor Parameter Editor Settings with Reset Agent Set to On-Chip Flash
- Click Generate HDL when the Generation dialog box appears.
- Specify output file generation options and click Generate.
Quartus® Prime Software Settings
- In the Quartus® Prime software, click Assignments > Device > Device and Pin Options > Configuration. Set the Configuration mode according to the setting in On-Chip Flash IP.
Figure 59. Configuration Mode Selection in Quartus® Prime Software
- Click OK to exit the Device and Pin Options window,
- Click OK to exit the Device window.
- Click Processing > Start Compilation to compile your project and generate the .sof file.
Note: If the configuration mode setting in Quartus® Prime software and Platform Designer parameter editor is different, the Quartus® Prime project fails with the following error message.
Figure 60. Error Message for Different Configuration Mode Setting
Error (14740): Configuration mode on atom "q_sys:q_sys_inst|altera_onchip_flash:onchip_flash_1| altera_onchip_flash_block:altera_onchip_flash_block|ufm_block" does not match the project setting. Update and regenerate the Qsys system to match the project setting.