1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
2.8. Optimizing Platform Designer System Performance
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from On-Chip Flash (UFM)
4.6. Nios® V Processor Booting from General Purpose QSPI Flash
4.7. Nios® V Processor Booting from Configuration QSPI Flash
4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.10. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.11. Reducing Nios® V Processor Booting Time
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
2.3.1.4.3. Defining Address Span Extender Linker Memory Device
- Define the Address Span Extender (EMIF) as the reset vector. Alternatively, you can assign the Nios® V processor reset vector to other memories, such as OCRAM or flash devices.
Figure 17. Multiple Options as Reset Vector
However, the Board Support Package (BSP) Editor cannot automatically register the Address Span Extender (EMIF) as a valid memory. Depending on the choice you made, you see two different situations as shown in the following figures.
Figure 18. BSP Error when Defining Address Span Extender (EMIF) as Reset VectorFigure 19. Missing EMIF when Defining Other Memories as Reset Vector - You must manually add the Address Span Extender (EMIF) using Add Memory Device, Add Linker Memory Region, and Add Linker Section Mappings in the BSP Linker Script tab.
- Follow these steps:
- Determine the address span of the Address Span Extender using the Memory Map (The example in the following figure uses Address Span Extender range from 0x0 to 0x3fff_ffff).
Figure 20. Memory Map
- Click Add Memory Device, and fill in based on the information in your design’s Memory Map:
- Device Name: emif_ddr4.
Note: Ensure you copy the same name from Memory Map.
- Base Address: 0x0
- Size: 0x40000000
- Device Name: emif_ddr4.
- Click Add to add a new linker memory region:
Table 22. Adding Linker Memory Region Steps Reset Vector emif_ddr4 Other memories 1 Add a new Linker Memory Region called reset.
- Region Name: reset
- Region Size: 0x20
- Memory Device: emif_ddr4
- Memory Offset: 0x0
Add a new Linker Memory Region for the emif_ddr4.
- Region Name: emif_ddr4
- Region Size: 0x40000000
- Memory Device: emif_ddr4
- Memory Offset: 0x0
2 Add a new Linker Memory Region for the remaining emif_ddr4.
- Region Name: emif_ddr4
- Region Size: 0x3fffffe0
- Memory Device: emif_ddr4
- Memory Offset: 0x20
Figure 21. Linker Region when Defining Address Span Extender (EMIF) as Reset VectorFigure 22. Linker Region when Defining Other Memories as Reset Vector - Once the emif_ddr4 is added to the BSP, you can select it for any Linker Section.
Figure 23. Added Address Span Extender (EMIF) Successfully
- Ignore the warning about Memory device emif_ddr4 is not visible in the SOPC design.
- Proceed to Generate BSP.
- Determine the address span of the Address Span Extender using the Memory Map (The example in the following figure uses Address Span Extender range from 0x0 to 0x3fff_ffff).
Related Information