1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
2.8. Optimizing Platform Designer System Performance
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from On-Chip Flash (UFM)
4.6. Nios® V Processor Booting from General Purpose QSPI Flash
4.7. Nios® V Processor Booting from Configuration QSPI Flash
4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.10. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.11. Reducing Nios® V Processor Booting Time
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
5.7.2. Configuring MAC and IP Addresses
You can configure the MAC and IP addresses of the µC/TCP-IP module by editing the struct network_conf conf in software/app/main.c source code.
If a DHCP server is available on your network, enable the DHCP feature by modifying the use_dhcp field to true (DEF_TRUE). If the DHCP feature is enabled, the provided IP addresses, network mask, and gateway are left unused. It is not required to clear their contents.
If the development board is connected directly to your PC with a crossover Ethernet cable, or no DHCP server is available, disable the DHCP feature (!DEF_TRUE) and specify the IP addresses, network mask, and gateway.
Default “struct network_conf conf” in main.c
struct network_conf conf = { .tse_sys_info = tse_sys_info, .mac_addr = "00:07:ed:ff:8c:05", .use_dhcp = !DEF_TRUE, .ipv4_addr_str = "192.168.1.45", .ipv4_mask_str = "255.255.255.0", .ipv4_gateway_str = "192.168.1.1" };
Note:
- Choose your default IP and gateway addresses carefully. Some secure router configurations block DHCP request packets on local subnetworks such as the 192.168.X.X subnetwork. If you encounter problems, try using 0.0.0.0 as your default IP and gateway addresses.
- You can configure the DHCP waiting time (DHCP_WAIT_MS) in the uc_tcp_ip_init.c source code. The DHCP waiting time is the amount of time delayed before verifying that a valid IP address is acquired by the TSE IP.