F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide
ID
720998
Date
4/12/2022
Public
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2.5. TX and RX PMA Status Signals
The following table describes the TX and RX PMA status signals that are a part of the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP.
Signal Name | Clocks Domain/Resets | Direction | Description |
---|---|---|---|
fgt_tx_beacon[N-1:0] | Asynchronous | Input | 1'b1: enable SATA beacon signal. 1'b0: disable SATA beacon signal. |
tx_pll_locked[N-1:0] | Asynchronous | Output | TX channel PLL locked signal for both FGT and FHT to reference clock within the PPM threshold status signal for fast/medium or slow PLL. 1’b1 = locked. 1’b0 = not locked. |
tx_dsk_valid[M-1:0] | Asynchronous | Output | Indicate a successful deskew, only used for multi-lane FEC direct mode |
Signal Name | Clocks Domain/Resets | Direction | Description |
---|---|---|---|
fgt_rx_signal_detect[N-1:0] | Asynchronous | Output | FGT RX signal detect indicator. |
fgt_rx_signal_detect_lfps[N-1:0] | Asynchronous | Output | Indicates SATA low frequency periodic signaling (LFPS) signal detection. |
rx_is_lockedtoref[N-1:0] | Asynchronous | Output | CDR lock status signal.
When lockedtodata stays high, the lockedtoref signal status is insignificant. |
rx_is_lockedtodata[N-1:0] | Asynchronous | Output | RX CDR data lock status signal.
When asserted, indicates that the CDR is in locked-to-data mode. When continuously asserted and does not switch between asserted and deasserted, you can confirm that the CDR is actually locked to data. |
fgt_rx_set_locktoref[N-1:0] | Asynchronous | Input | 1'b1: keep CDR in lock to reference mode. 1'b0: keep CDR in auto mode. |
fgt_rx_cdr_freeze[N-1: 0] | Asynchronous | Input | This port is used in GPON to freeze the CDR lock state during inactive time-slots. |