F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

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ID 720998
Date 4/12/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

2.9. Datapath Avalon Memory-Mapped Signals

The following table describes the Datapath Avalon® memory-mapped signals that are a part of the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP.

Table 16.  Datapath Avalon® Memory-Mapped Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
reconfig_pdp_clk N/A Input Reconfig Interface Clock
reconfig_pdp_reset reconfig_pdp_clk Input Reconfiguration Interface Reset
reconfig_pdp_address[13+K d :0] reconfig_pdp_clk Input Reconfig Interface Address. K d=Ceiling(log2(N)). Word address. EMIB core adapter and soft CSR registers use unused space of F-tile Datapath Avalon® memory mapped 16-bit address.
reconfig_pdp_byteenable [3:0] reconfig_pdp_clk Input Byte Enable. If byteenable[3:0] is 4’b1111, 32-bit Dword Access is assumed; otherwise byte access is used.
reconfig_pdp_write reconfig_pdp_clk Input Reconfig Write
reconfig_pdp_read reconfig_pdp_clk Input Reconfig Read
reconfig_pdp_writedata [31:0] reconfig_pdp_clk Input Reconfig Write data
reconfig_pdp_readdata [31:0] reconfig_pdp_clk Output Reconfig Read data
reconfig_pdp_waitrequest reconfig_pdp_clk Output Reconfig Wait Request
reconfig_pdp_readdatavalid reconfig_pdp_clk Output Reconfig Read Data Valid. Optional port, available if the port is enabled in parameter editor.
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