F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

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ID 720998
Date 4/12/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

6. Configuration Registers Overview

You can access the registers for the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP core using the Datapath Avalon® memory-mapped interface .

The dynamic reconfiguration soft CSR registers are used for switching profiles within a reconfiguration group. You need to write and update the dynamic reconfiguration soft CSR registers to ensure a successful dynamic reconfiguration process.

To enable the static soft CSR and reconfiguration soft CSR registers, you must select the Enable datapath Avalon interface, Enable soft CSR and Enable reconfiguration soft CSR parameters in the Datapath Avalon memory-mapped interface section of the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP core.

This chapter only describes the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP related reconfiguration soft CSR registers. For description of the static F-Tile PMA and FEC Direct PHY Intel FPGA IP soft CSR registers, refer to the F-Tile Architecture and PMA and FEC Direct PHY Intel FPGA IP User Guide.


Section Content
Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration
Configuration Registers

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