F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

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ID 720998
Date 4/12/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

2.1. Clock Signals

The following table describes the clock signals that are a part of the clock interface of the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP.
Table 7.  TX and RX Reference Clock and Clock Output Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description

rx_clkout_stream<x>

rx_clkout2_stream<x>

tx_clkout_stream<x>

tx_clkout2_stream<x>

N/A Output Output port enabled by default. You can select one of these ports, by selecting TX/RX clock options. These are per stream in F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP as interfaces in the system mode requires clock signals to be single bit per clock.

tx_coreclkin

N/A Input The FPGA core clock that drives the write side of TX FIFO.
rx_coreclkin N/A Input

The FPGA core clock that drives the read side of RX FIFO.

tx_pll_refclk_link_xcvr<n>_prof<j> N/A Input These clock ports are 1 bit. This is neither physical nor logical port. You connect this to <out_refclk_fgt<x>> port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP. This connection guides Intel® Quartus® Prime Pro Edition software to correctly configure the clock network.
rx_cdr_refclk_link_xcvr<n>_prof<j> N/A Input These clock ports are 1 bit. This is neither physical nor logical port. You connect this to <out_refclk_fgt<x>> port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP. This connection guides Intel® Quartus® Prime Pro Edition software to correctly configure the clock network.
system_pll_clk_link N/A Input This is virtual representation of system PLL output clock. This is neither physical nor logical port. You connect this to <out_systempll_clk_0> port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP. This connection guides Intel® Quartus® Prime Pro Edition software to correctly configure the clock network.
Note: Ports ending in _link must connect to the F-Tile Reference and System PLL Clocks Intel® FPGA IP. These ports cannot be simulated.
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