F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

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ID 720998
Date 4/12/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

1.5. Resource Utilization

These results were obtained using the Intel® Quartus® Prime software version 22.1 with the following conditions:
  • The resource utilization is specific to FGT reconfiguration groups.
  • The resource utilization excludes the soft logic utilization for the *_Tiles file, generated by Intel® Quartus® Prime software after the support logic generation phase.
    Note: The IP currently only supports FGT PMA reconfiguration.
Table 4.  Resource Utilization for Intel® Agilex™ Devices
Reconfiguration Group ALMs Combinatorial ALUTs Logic Registers Block Memory Bits
25GE-1 PMA mode 465 536 482 0
25GE-1 FEC mode 461 540 484 0
50GE-1 PMA mode 602 670 499 0
50GE-1 FEC mode 599 674 499 0
50GE-2 PMA mode 833 1062 707 0
50GE-2 FEC mode 827 1061 748 0
100GE-2 PMA mode 1377 1790 958 0
100GE-2 FEC mode 1351 1793 981 0
100GE-4 PMA mode 931 1,118 851 0
100GE-4 FEC mode 1,596 1,952 1,500 0
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