F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

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ID 720998
Date 4/12/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core

The F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP parameter settings are similar to the single rate F-Tile PMA/FEC Direct PHY Intel FPGA IP except some parameters and ports are not applicable and hence not visible in the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP GUI.

The F-Tile PMA/FEC Direct Multi-Rate PHY Intel FPGA IP has additional parameters such as Reconfiguration group, Configuration subset, Number of secondary profiles, Master PMA target for profile, Profile group id and Use profile for startup for setting up the reconfiguration profiles.

The secondary profile must use all of the PMA lanes allocated for the reconfiguration group, either within a single profile or in multiple profiles by using the same Profile group id. The same parameter settings selected for Profile #N IP Configuration can be reused within the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP with different Common Datapath Options PN (N=0-15), TX Datapath Options PN (N=0-15), RX Datapath Options PN (N=0-15) or RS-FEC PN (N=0-15) settings.

You can have Profile #1 with RS-FEC disabled, using the Profile #1 IP Configuration settings for Profile #1 as;
  • Configuration subset = 2x50GE-1
  • Master PMA target for profile = 0
  • Profile group id = 1
  • Enable RS-FEC use = On
  • Enable RS-FEC = Off
You can configure Profile #2 with the same Profile #2 IP Configuration settings with RS-FEC enabled;
  • Configuration subset = 2x50GE-1
  • Master PMA target for profile = 0
  • Profile group id = 1
  • Enable RS-FEC use = On
  • Enable RS-FEC = On

Section Content
Steps to Configure the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core

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