F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide
ID
720998
Date
4/12/2022
Public
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2.7. TX and RX PMA FIFO Signals
The following table describes the TX and RX PMA Interface FIFO signals that are a part of the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP.
Note: The tx_pmaif_fifo ports and rx_pmaif_fifo ports are only selectable in the base profile (Profile #0).
Signal Name | Clocks Domain/Resets | Direction | Description |
---|---|---|---|
tx_pmaif_fifo_empty[(N*X)-1:0] | Asynchronous | Output | PMA Interface TX FIFO empty. |
tx_pmaif_fifo_pempty[(N*X)-1:0] | Asynchronous | Output | PMA Interface TX FIFO partially empty. |
tx_pmaif_fifo_pfull[(N*X)-1:0] | Asynchronous | Output | PMA Interface TX FIFO partially full. |
tx_pmaif_fifo_overflow[(N*X)-1:0] | Asynchronous | Output | PMA Interface TX FIFO overflow. |
rx_pmaif_fifo_empty[(N*X)-1:0] | Asynchronous | Output | PMA Interface RX FIFO empty. |
rx_pmaif_fifo_pempty[(N*X)-1:0] | Asynchronous | Output | PMA Interface RX FIFO partially empty. |
rx_pmaif_fifo_pfull[(N*X)-1:0] | Asynchronous | Output | PMA Interface RX FIFO partially full. |