F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

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ID 720998
Date 4/12/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multi-Rate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. Document Revision History for the F-Tile PMA and FEC Direct PHY Multi-Rate Intel® FPGA IP User Guide

1.1.5. Supported Reconfiguration Groups

This section specifies the supported reconfiguration groups for FGT PMA.

The Configuration subset defines a portion of the fracture set within the Reconfiguration group. The available subsets such as 100GE, 50GE and 25GE are the fracture types that you can select from F-tile. For more information about the fracture types, refer to F-Tile Architecture and PMA and FEC Direct PHY Intel FPGA IP User Guide.

Table 1.  Available Reconfiguration Groups for FGT PMA
Reconfiguration Group Configuration Subset Maximum Number of Lanes Modulation System PLL Frequency (in MHz) PMA Type
100GE-4 Reconfigurable

1x100GE-4

2x50GE-2

4x25GE-1

 4 NRZ/PAM4 830.078125 FGT

100GE-2 Reconfigurable

1x100GE-2

2x50GE-1

1x50GE-2

2x25GE-1

 2 NRZ/PAM4 830.078125 FGT

50GE-2 Reconfigurable

1x50GE-2

2x25GE-1

 2 NRZ/PAM4 830.078125 FGT

50GE-1 Reconfigurable

1x50GE-1

1x25GE-1

 1 NRZ/PAM4 830.078125 FGT

25GE-1 Reconfigurable

1x25GE-1

 1 NRZ/PAM4 830.078125 FGT
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