F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Precision Time Protocol Interface
2.15. Precision Time Protocol Interface x
2.15.1. PTP Clock Interface 2.15.2. Time-of-Day Interface 2.15.3. TX 2-Step Timestamp Interface 2.15.4. TX 1-Step Timestamp Interface 2.15.5. RX Timestamp Interface 2.15.6. PTP Status Interface 2.15.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.15.4. TX 1-Step Timestamp Interface

A separate TX 1-step timestamp interface is available for each supported port within a reconfiguration group. The below table shows the interface details for different number of ports.

For 400GE rate, width of TX 1-step timestamp is 2x of other Ethernet rates. The interface signals of port 2 and port 0 are concatenated for 400GE port 0 usage as below: 
{msb, lsb} == {i_p2_ptp_<signals>, i_p0_ptp_<signals>}
The table describes the interface details for different number of ports.
Table 69.  Signals of the 1-Step TX Timestamp InterfaceFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Maximum Number of Ports Applicable Reconfiguration Groups Signal Name
1

FGT:

25GE-1 Reconfigurable

50GE-1 Reconfigurable

FHT:

50GE-1 Reconfigurable

100GE-1 Reconfigurable

Port 0:

i_p0_ptp_ins_ets

i_p0_ptp_ins_cf

i_p0_ptp_zero_csum

i_p0_ptp_update_eb

i_p0_ptp_p2p

i_po_ptp_asym

i_po_ptp_asym_sign

i_po_ptp_asym_p2p_idx[6:0]

i_po_ptp_ts_offset[15:0]

i_po_ptp_cf_offset[15:0]

i_po_ptp_csum_offset[15:0]

i_po_ptp_tx_its[95:0]

2

FGT:

100GE-2 Reconfigurable

FHT:

100GE-2 Reconfigurable

200GE-2 Reconfigurable

Port 0:

i_p0_ptp_ins_ets

i_p0_ptp_ins_cf

i_p0_ptp_zero_csum

i_p0_ptp_update_eb

i_p0_ptp_p2p

i_po_ptp_asym

i_po_ptp_asym_sign

i_po_ptp_asym_p2p_idx[6:0]

i_po_ptp_ts_offset[15:0]

i_po_ptp_cf_offset[15:0]

i_po_ptp_csum_offset[15:0]

i_po_ptp_tx_its[95:0]

Port 1:

i_p1_ptp_ins_ets

i_p1_ptp_ins_cf

i_p1_ptp_zero_csum

i_p1_ptp_update_eb

i_p1_ptp_p2p

i_p1_ptp_asym

i_p1_ptp_asym_sign

i_p1_ptp_asym_p2p_idx[6:0]

i_p1_ptp_ts_offset[15:0]

i_p1_ptp_cf_offset[15:0]

i_p1_ptp_csum_offset[15:0]

i_p1_ptp_tx_its[95:0]

4

FGT:

100GE-4 Reconfigurable

400GE-8 Reconfigurable

200GE-4 Reconfigurable

FHT:

100GE-4 Reconfigurable

400GE-4 Reconfigurable

200GE-4 Reconfigurable

Port 0:

i_p0_ptp_ins_ets

i_p0_ptp_ins_cf

i_p0_ptp_zero_csum

i_p0_ptp_update_eb

i_p0_ptp_p2p

i_po_ptp_asym

i_po_ptp_asym_sign

i_po_ptp_asym_p2p_idx[6:0]

i_po_ptp_ts_offset[15:0]

i_po_ptp_cf_offset[15:0]

i_po_ptp_csum_offset[15:0]

i_po_ptp_tx_its[95:0]

Port 1:

i_p1_ptp_ins_ets

i_p1_ptp_ins_cf

i_p1_ptp_zero_csum

i_p1_ptp_update_eb

i_p1_ptp_p2p

i_p1_ptp_asym

i_p1_ptp_asym_sign

i_p1_ptp_asym_p2p_idx[6:0]

i_p1_ptp_ts_offset[15:0]

i_p1_ptp_cf_offset[15:0]

i_p1_ptp_csum_offset[15:0]

i_p1_ptp_tx_its[95:0]

Port 2:

i_p2_ptp_ins_ets

i_p2_ptp_ins_cf

i_p2_ptp_zero_csum

i_p2_ptp_update_eb

i_p2_ptp_p2p

i_p2_ptp_asym

i_p2_ptp_asym_sign

i_p2_ptp_asym_p2p_idx[6:0]

i_p2_ptp_ts_offset[15:0]

i_p2_ptp_cf_offset[15:0]

i_p2_ptp_csum_offset[15:0]

i_p2_ptp_tx_its[95:0]

Port 3:

i_p3_ptp_ins_ets

i_p3_ptp_ins_cf

i_p3_ptp_zero_csum

i_p3_ptp_update_eb

i_p3_ptp_p2p

i_p3_ptp_asym

i_p3_ptp_asym_sign

i_p3_ptp_asym_p2p_idx[6:0]

i_p3_ptp_ts_offset[15:0]

i_p3_ptp_cf_offset[15:0]

i_p3_ptp_csum_offset[15:0]

i_p3_ptp_tx_its[95:0]

Level Two Title