F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 12/19/2022
Public

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2.3. Reset Signals

Each of the Ethernet Multirate IP core ports has its own set of reset signals. The i_reconfig_reset reset signal is shared. The rx_pcs_ready and tx_lanes_stable signals are available on per port basis.
Table 15.  Reset SignalsAll specified resets are asynchronous.
Port Name Number of Ports I/O Direction Description
i_reconfig_reset 1, 2, or 4 Input Reconfiguration reset. Resets the Avalon® memory-mapped interface connections to the F-tile and resets Soft CSR. It does not reset F-tile CSRs. Active high. Must be asserted once upon power-up.
i_p0_rst_n 1, 2, or 4 Input

Active-low reset asynchronous signal.

This reset leads to assertion of the o_p0_rst_ack_n output signal.

Do not deassert until the o_p0_rst_ack_n output signal deasserts.

  • Resets the TX interface, including the TX PMA, TX PCS, TX MAC, and TX AIB.
  • Resets the RX interface, including the RX PMA, RX PCS, RX MAC, and RX AIB.
o_p0_rst_ack_n 1, 2, or 4 Output

Acknowledgement signal for the i_p0_rst_n reset. Active low.

i_p0_tx_rst_n 1, 2, or 4 Input Resets the selected port 0 TX datapath. Active low.
o_p0_tx_rst_ack_n 1, 2, or 4 Output Port 0 TX datapath reset acknowledgement. Active low.
i_p0_rx_rst_n 1, 2, or 4 Input Resets the selected port 0 RX datapath. Active low.
o_p0_rx_rst_ack_n 1, 2, or 4 Output Port 0 RX datapath reset acknowledgement. Active low.
o_p0_tx_lanes_stable 1, 2, or 4 Output Port 0 TX datapath is out of reset and ready.
o_p0_rx_pcs_ready 1, 2, or 4 Output Port 0 RX datapath is out of reset and ready.
i_p1_rst_n 2 or 4 Input

Active-low reset asynchronous signal.

This reset leads to assertion of the o_p1_rst_ack_n output signal.

Do not deassert until the o_p1_rst_ack_n output signal deasserts.

  • Resets the TX interface, including the TX PMA, TX PCS, TX MAC, and TX AIB.
  • Resets the RX interface, including the RX PMA, RX PCS, RX MAC, and RX AIB.
o_p1_rst_ack_n 2 or 4 Output

Acknowledgement signal for the i_p1_rst_n reset. Active low.

i_p1_tx_rst_n 2 or 4 Input Resets the selected port 1 TX datapath. Active low.
o_p1_tx_rst_ack_n 2 or 4 Output Port 1 TX datapath reset acknowledgement. Active low.
i_p1_rx_rst_n 2 or 4 Input Resets the selected port 1 RX datapath. Active low.
o_p1_rx_rst_ack_n 2 or 4 Output Port 1 RX datapath reset acknowledgement. Active low.
o_p1_tx_lanes_stable 2 or 4 Output Port 1 TX datapath is out of reset and ready.
o_p1_rx_pcs_ready 2 or 4 Output Port 1 RX datapath is out of reset and ready.
i_p2_rst_n 4 Input

Active-low reset asynchronous signal.

Active-low reset asynchronous signal. This reset leads to assertion of the o_p2_rst_ack_n output signal.

Do not deassert until the o_p2_rst_ack_n output signal deasserts.

  • Resets the TX interface, including the TX PMA, TX PCS, TX MAC, and TX AIB.
  • Resets the RX interface, including the RX PMA, RX PCS, RX MAC, and RX AIB.
o_p2_rst_ack_n 4 Output

Acknowledgement signal for the i_p2_rst_n reset. Active low.

i_p2_tx_rst_n 4 Input Resets the selected port 2 TX datapath. Active low.
o_p2_tx_rst_ack_n 4 Output Port 2 TX datapath reset acknowledgement. Active low.
i_p2_rx_rst_n 4 Input Resets the selected port 2 RX datapath. Active low.
o_p2_rx_rst_ack_n 4 Output Port 2 RX datapath reset acknowledgement. Active low.
o_p2_tx_lanes_stable 4 Output Port 2 TX datapath is out of reset and ready.
o_p2_rx_pcs_ready 4 Output Port 2 RX datapath is out of reset and ready.
i_p3_rst_n 4 Input

Active-low reset asynchronous signal.

This reset leads to assertion of the o_p3_rst_ack_n output signal.

Do not deassert until the o_p3_rst_ack_n output signal deasserts.

  • Resets the TX interface, including the TX PMA, TX PCS, TX MAC, and TX AIB.
  • Resets the RX interface, including the RX PMA, RX PCS, RX MAC, and RX AIB.
o_p3_rst_ack_n 4 Output

Acknowledgement signal for the i_p3_rst_n reset. Active low.

i_p3_tx_rst_n 4 Input Resets the selected port 3 TX datapath. Active low.
o_p3_tx_rst_ack_n 4 Output Port 3 TX datapath reset acknowledgement. Active low.
i_p3_rx_rst_n 4 Input Resets the selected port 3 RX datapath. Active low.
o_p3_rx_rst_ack_n 4 Output Port 3 RX datapath reset acknowledgement. Active low.
o_p3_tx_lanes_stable 4 Output Port 3 TX datapath is out of reset and ready.
o_p3_rx_pcs_ready 4 Output Port 3 RX datapath is out of reset and ready.