F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.15.7. PTP Tile Interface

A 1-bit ptp_link signal is available per each F-tile Ethernet Multirate IP core. When PTP is enabled, you must connect the PTP link port of one or more Ethernet Multirate IP to the PTP Tile Adapter. The Support Logic Generation step in the Intel® Quartus® Prime software automatically generates the actual PTP signals between the F-Tile Ethernet Multirate IP core's PTP soft logic and the PTP tile adapter.

Note: When PTP is enabled, F-tile Ethernet Multirate IP automatically generates the F-tile PTP adapter.
The table displays the interface details for different numbers of ports.
Table 72.  Signals of the PTP Tile InterfaceFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Maximum Number of Ports Signal Name
1, 2, or 4 ptp_link