F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 12/19/2022
Public

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1.8.8. Transceiver Lane Mapping

The transceiver lane mapping defines a predictable mapping to the EMIBs or demaping from the EMIBs. Transceiver lane mappings specifies transceiver lane assignments for each supported profile within a reconfiguration group.

The below restriction tables specify the maximum number of ports and the maximum number of transceiver lanes defined for each reconfiguration group.

Table 8.  Reconfiguration Group Restrictions using Two Transceiver Lanes
Transceiver Lane /

Number of ports

FGT / FHT1 FGT / FHT0
1 port using 2 lanes Port 0, Lane 0 Port 0, Lane 1
2 ports using 1 lane each Port 0, Lane 0 Port 1, Lane 0

Table 9.  Reconfiguration Group Restrictions Using Four Transceiver Lanes
Note: All 4x lanes must be part of a single FGT QUAD.
Transceiver Lane /

Number of ports

FGT / FHT3 FGT / FHT2 FGT / FHT1 FGT / FHT0
1 port using 4 lanes Port 0, Lane 0 Port 0, Lane 1 Port 0, Lane 2 Port 0, Lane 3
1 port using 2 lanes Port 0, Lane 0 Port 0, Lane 1 Unused Unused
1 port using 1 lane Port 0, Lane 0 Unused Unused Unused
2 ports using 2 lanes each Port 0, Lane 0 Port 0, Lane 1 Port 2, Lane 0 Port 2, Lane 1
2 ports using 1 lane each Port 0, Lane 0 Port 2, Lane 0 Unused Unused
4 ports using 1 lane each Port 0, Lane 0 Port 1, Lane 0 Port 2, Lane 0 Port 3, Lane 0
Table 10.  Reconfiguration Group Restrictions Using Eight Transceiver Lanes
Note: All 8x lanes must be assigned to two adjoining QUADs.
Transceiver Lane /

Number of ports

FGT7 FGT6 FGT5 FGT4 FGT3 FGT2 FGT1 FGT0
1 port using 8 lanes Port 0, Lane 0 Port 0, Lane 1 Port 0, Lane 2 Port 0, Lane 3 Port 0, Lane 4 Port 0, Lane 5 Port 0, Lane 6 Port 0, Lane 7
2 ports using 4x lanes each Port 0, Lane 0 Port 0, Lane 1 Port 0, Lane 2 Port 0, Lane 3 Port 2, Lane 0 Port 2, Lane 1 Port 2, Lane 2 Port 2, Lane 3
4 ports using 2x lanes each Port 0, Lane 0 Port 0, Lane 1 Port 1, Lane 0 Port 1, Lane 1 Port 2, Lane 0 Port 2, Lane 1 Port 3, Lane 0 Port 3, Lane 1