F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Precision Time Protocol Interface
2.15. Precision Time Protocol Interface x
2.15.1. PTP Clock Interface 2.15.2. Time-of-Day Interface 2.15.3. TX 2-Step Timestamp Interface 2.15.4. TX 1-Step Timestamp Interface 2.15.5. RX Timestamp Interface 2.15.6. PTP Status Interface 2.15.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.12.19 22.4 5.0.0 Added the following in Parameters section:
  • Added PTP limitations when using FM4 devices in Device Speed Grade Support.
  • Include 32-bit soft CWBIN counters parameter.
  • PTP support for MAC Avalon ST client interface parameter.
  • PTP logic resource optimization.
  • Reconfig Clock Frequency.
  • Added the IP parameter Editor: PTP options tab image in Parameters.
  • Added a new register preamble_passthrough[3:0] with offset 0x20C in Configuration Registers section.
2022.10.20 22.3 4.0.0 Added the following:
  • Added Available Reconfiguration groups Using FHT Transceivers table in Supported Reconfiguration Groups.
  • Added Timestamp Accuracy Support for FHT Transceivers in PTP Timestamp Accuracy Support.
Added the following in Interface Overview section:
  • Added i_clk_pll input clock signals in Clock Signals section.
  • Updated the description for reset signals i_p0_rst_n in Reset Signals.
  • Supported Timestamp Accuracy Modes per Profile table for FHT reconfiguration groups in PTP Clock Interface.
  • Fractured MAC Segmented Interface for FHT Transceivers in Interface Overview.
  • Fractured MAC Avalon ST Client Interface for FHT Transceivers in Interface Overview.
  • Fractured MII PCS-Only Interface for FHT Transceivers Interface Overview.
  • Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers in Interface Overview.
  • Signals of the Precision Time Protocol (PTP) Interface in Precision Time Protocol Interface.
  • Signals of the Time-of-Day (TOD) Interface for FHT Reconfiguration Groups in Time-of-Day Interface.
  • Added FHT Reconfiguration Groups to signals of the PTP Status Interface table in PTP Status Interface.
Added the following in Parameters section.
  • FHT supports 50G-100G per lane.
  • Ready Latency parameter.
  • Enable TX Packing Parameter.
  • Enable asynchronous adapter clocks Parameter.
  • FHT startup profiles under Startup Profile Options.
  • Updated IP parameter Editor: IP tab image in Parameters.
  • Added Configure Reference Clock for FHT PMA in Reference ans System PLL Clock for your IP Design.
Added the following in Configuration Registers section.
  • Signal decoding for the FHT transceivers
  • Port-specific bit definitions for 0x208 offset.

Added Document Archive section.

2022.06.20 22.2 3.0.0 Added the following:
  • Footnote in parameters setting-IP tab table under PTP options.
  • The number of allowed ports-PTP GUI options table in Parameters section.
  • PTP Clock Interface topic in PTP interface.
  • Supported Timestamp Accuracy Modes per Profile table in PTP Clock Interface.
  • Compilation note F-tile Ethernet Multirate IP automatically generates the F-tile PTP adapter in PTP Tile Interface.
  • Limitations of PTP in F-Tile Ethernet Multirate IP Core Features and Constraints.
  • Added new topic Fractured MAC SOP-Aligned Client Interface for FGT Transceivers in Interface Overview.
  • Updated note in Device Speed Grade Support.
  • Updated PTP Status Interface table in PTP Interface.
  • Updated Release Information in Introduction section.
  • Updated i_reconfig_clk description in Clock Signals table:
    • When PTP is enabled, the i_reconfig_clk frequency supports the range of 100 to 250 MHz.
2022.04.04 22.1 2.0.0 Initial release.
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