2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Precision Time Protocol Interface
|Intel® Quartus® Prime Design Suite 22.4|
|IP Version 5.0.0|
The F-Tile Ethernet Multirate Intel® FPGA IP core is a multirate version of the F-Tile Ethernet Intel FPGA Hard IP core that supports the dynamic reconfiguration flow in the Intel® Agilex™ devices with F-tile. The IP core provides various options to specify the power up settings, and target dynamic reconfiguration profiles for your design.
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