F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 10/06/2023
Document Table of Contents

3.1.3. Ethernet Multirate Design Example: Reset Scheme

The i_reconfig_reset signal resets the soft registers of Ethernet Multirate Intel FPGA IP core and Dynamic Reconfiguration Controller IP. After power up and before starting dynamic reconfiguration sequences, this reset is asserted and released once. This reset must not be asserted afterwards.

The datapath resets, i_rst_n, i_tx_rst_n, and i_rx_rst_n must be asserted when performing dynamic reconfiguration.